This is going to be pretty esoteric for many of my readers, but in previous semiconductor posts covering ASML, some commenters have suggested that fabs can do multi-patterning for smaller nodes rather than having to use ASML’s extreme ultraviolet stepper. The following video explains why, below a certain threshold, no, you really can’t.
I’m not going to summarize every point, but the largest takeaway is that multi-patterning is computationally prohibitive. Double-patterning splits a single mask into two masks, each of which only create half of the mask pattern on the die. Double-patterning was fine for a while, but triple patterning and self-aligned double-patterning start making finding optimal solutions to the mask splitting problem exponentially more difficult.
Take a square. A square has four nodes in it. With double patterning, each of the two masks handle opposing sides of the square. And with this four-node shape, there are two double patterning options available for coloring. The EDA software thus has to check through them for design rule violations and whatnot. With triple patterning, the number of variations explodes exponentially. For that same square four node structure, triple patterning has 18 variations rather than just two with double patterning. A five node structure, 30. And so on. A semiconductor design can have hundreds of different nodes and design variations. The software needs to check through at least a good portion of these. This problem is not solvable in polynomial time. In other words, for you computer science nerds out there, it is an NP complete problem.
And then there’s the cost. “Depending on whose cost model you consult, [10nm]’s triple patterning makes its lithography module 3.85x higher than [28nm].” And the non-EUV 7nm node required triple-patterning and something called “self-aligned quadruple patterning.” And on Intel: “Brian Krzanich has said that in certain cases the company needs to use quad (4x), penta (5x), or hexa (6x) patterning for select features, as they need to expose the wafer up to six times to “draw” one feature. I am not super surprised that it wouldn’t yield. No wonder GlobalFoundries ditched their 7nm node.”
And this summary glosses over big differences between different fab technologies on different companies. TSMC’s 7nm isn’t the same as Intel’s 7nm.
Anyway, all this goes a long way to explain: Multi-patterning is much more painful than simply ponying up the cost for an ASML EUV stepper. And if you want to do 6nm, you have to use EUV.
Tags: ASML, EUV, GlobalFoundries, Intel, NP Complete, Semiconductors, technology, video